At the centre of this strategy is a concept Huawei calls the “Tau Scaling Law,” which reframes chip progress around latency reduction and system-level optimisation rather than continuing the decades-long race to shrink components.
“Moore’s Law is hitting a wall,” Huawei says
For decades, the semiconductor industry has advanced under the logic of Moore's Law, the observation that transistor density roughly doubles every two years. But Huawei argues that physical limits, combined with geopolitical restrictions, are forcing a rethink of that model.
"One is inevitable that Moore's Law will hit a physical 'wall' within the next decade," said He Tingbo, president of Huawei’s semiconductor division.
She also pointed to external constraints that have accelerated the pressure:
"The other is accidental because of the external restrictions that Huawei encountered this 'wall' earlier than its peers," she added, referring to U.S. export controls that restrict access to advanced lithography equipment.
Those restrictions include bans on importing extreme ultraviolet tools from ASML, which are essential for producing the most advanced chips and are widely used by leading manufacturers such as TSMC.
LogicFolding: stacking intelligence instead of shrinking transistors
Huawei’s technical answer is a design approach called “LogicFolding.” Instead of relying primarily on smaller process nodes, the method reorganises chip architecture by stacking logic, memory, and analogue components into more tightly integrated layers.
The goal is to reduce the time it takes for signals to travel through the system, potentially improving performance without requiring cutting-edge manufacturing nodes.
According to Huawei semiconductor chief scientist Liao Heng:
LogicFolding could go beyond conventional 3D integration by “very finely and carefully split[ting] the critical paths of logic circuits across multiple layers.”
In theory, this could increase efficiency, density, and clock speeds over time, particularly for AI workloads where data movement—not just computation—has become a major bottleneck.
Industry scepticism: innovation or repackaging?
Not everyone sees the approach as a paradigm shift. Critics argue that Huawei’s ideas closely resemble established methods already widely used in advanced chip design, particularly in three-dimensional stacking and heterogeneous integration.
Nvidia CEO Jensen Huang was blunt when assessing the claims:
"This is a breakthrough for Huawei, but it's not a threat for TSMC," he said in Taipei. "TSMC has been using die stacking and 3D packaging for how long now? Almost 10 years. And so TSMC's technology is very advanced."
Indeed, companies such as TSMC already use advanced packaging technologies like SoIC, while memory giants including SK Hynix and Samsung Electronics have long deployed multi-layer stacking to improve performance and efficiency in high-bandwidth memory systems.
Engineering limits: heat, cost, and yield risks
Even supporters acknowledge that stacking-based approaches introduce serious engineering trade-offs. Increasing vertical density can raise power concentration, making overheating more difficult to manage. Manufacturing yields can also decline as designs become more complex, driving up costs.
Analysts at Bernstein noted that while 3D stacking increases transistor density, it can also create thermal and manufacturing bottlenecks that are difficult to overcome at scale.
Huawei itself has acknowledged similar constraints, stating that the approach will require new design tools, improved thermal management, and broader system-level optimisation—especially for demanding environments such as AI data centres.
A shift in how chips are designed, not just built
Beyond hardware challenges, the approach could also reshape the software ecosystem that supports chip development. Industry figures suggest that shifting focus from chip-level optimisation to system-level timing would significantly affect electronic design automation (EDA) tools used by engineers.
As Handel H. Jones of International Business Strategies noted, such a shift could “dramatically change the capability requirements” for firms like Cadence Design Systems and Synopsys, which provide the core software used to design modern chips.
Kirin chip as first test case
Huawei’s most concrete near-term claim is a new Kirin chip for smartphones, expected later this year, which will reportedly be the first to implement LogicFolding.
According to company claims, the design could deliver up to a 41% improvement in power efficiency and nearly a 13% increase in peak operating speed compared with previous single-layer designs.
If achieved at scale, those gains would be meaningful in mobile and AI workloads. However, independent verification remains limited, and Huawei has not released detailed data on yields, costs, or comparisons with chips produced on more advanced manufacturing nodes.
As analyst Lian Jye Su of Omdia put it:
"There's nothing concrete that can be independently verified or benchmarked against other players at the moment."
Bigger picture: a strategic pivot under pressure
Huawei’s push reflects a broader reality in the global semiconductor race: as physical scaling becomes harder and geopolitical restrictions tighten, chip innovation is increasingly shifting toward architecture, packaging, and system design rather than transistor shrinkage alone.
Whether “Tau Scaling” becomes a genuine alternative pathway—or remains an incremental extension of existing 3D integration techniques—will depend less on theory and more on whether it can survive the realities of heat, cost, manufacturing yield, and global competition.